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INTEGRATED CIRCUITS
DATA SHEET
74ALVC125 Quad buffer/line driver; 3-state
Product specification 2002 Nov 18
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
FEATURES * Wide supply voltage range from 1.65 to 3.6 V * Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V) * 3.6 V tolerant inputs/outputs * CMOS low power consumption * Direct interface with TTL levels (2.7 to 3.6 V) * Power-down mode * Latch-up performance exceeds 250 mA * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs nA to output nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 CI CPD input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 outputs enable outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. DESCRIPTION
74ALVC125
The 74ALVC125 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74ALVC125 consists of four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on pin nOE causes the outputs to assume a high-impedance OFF-state.
TYPICAL 2.4 1.7 2.0 1.8 3.5 27 5 ns ns ns ns
UNIT
pF pF pF
2002 Nov 18
2
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
ORDERING INFORMATION PACKAGE TYPE NUMBER PINS 74ALVC125D 74ALVC125PW FUNCTION TABLE See note 1. INPUT nOE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1A 1Y 2OE 2A 2Y GND 3Y 3A 3OE 4Y 4A 4OE VCC SYMBOL 1OE data input bus output output enable input (active LOW) data input bus output ground (0 V) bus output data input output enable input (active LOW) bus output data input output enable input (active LOW) supply voltage DESCRIPTION output enable input (active LOW) nA L H X 14 14 PACKAGE SO14 TSSOP14 MATERIAL plastic plastic
74ALVC125
CODE SOT108-1 SOT402-1
OUTPUT nY L H Z
2002 Nov 18
3
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74ALVC125
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
MNA226
14 VCC 13 4OE 12 4A
handbook, halfpage
nA
nY
125
11 4Y 10 3OE 9 3A nOE
MNA227
8 3Y
Fig.1 Pin configuration.
Fig.2 Logic diagram (one buffer).
handbook, halfpage
2
handbook, halfpage
1A 1OE 2A 2OE 3A 3OE 4A 4OE
1Y
3
2 1 5 EN1
1
3
1 5
2Y
6
6 4 9 8 10 12 11 13
MNA229 MNA228
4 9 10 12 13
3Y
8
4Y
11
Fig.3 IEE/IEC logic symbol.
Fig.4 Logic symbol.
2002 Nov 18
4
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO PARAMETER supply voltage input voltage output voltage CONDITIONS 0 VCC = 1.65 to 3.6 V; enable mode 0 VCC = 1.65 to 3.6 V; disable mode 0 VCC = 0 V; Power-down mode Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 to 2.7 V VCC = 2.7 to 3.6 V 0 -40 0 0 MIN. 1.65
74ALVC125
MAX. 3.6 3.6 VCC 3.6 3.6 +85 20 10 V V V V V C
UNIT
ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO PARAMETER supply voltage input diode current input voltage output diode current output voltage VO > VCC or VO < 0 enable mode; notes 1 and 2 disable mode Power-down mode; note 2 IO ICC, IGND Tstg Ptot output source or sink current VCC or GND current storage temperature power dissipation SO package TSSOP package Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. above 70 C derate linearly with 8 mW/K above 60 C derate linearly with 5.5 mW/K - - 500 500 mW mW VO = 0 to VCC VI < 0 CONDITIONS - -0.5 - -0.5 -0.5 -0.5 - - -65 MIN. -0.5 MAX. +4.6 -50 +4.6 50 VCC + 0.5 +4.6 +4.6 50 100 +150 V mA V mA V V V mA mA C UNIT
2002 Nov 18
5
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C VIH HIGH-level input voltage 1.65 to 1.95 0.65 x VCC - 2.3 to 2.7 2.7 to 3.6 VIL LOW-level input voltage 2.3 to 2.7 2.7 to 3.6 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 6 mA IO = 12 mA IO = 18 mA IO = 12 mA IO = 18 mA IO = 24 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -6 mA IO = -12 mA IO = -18 mA IO = -12 mA IO = -18 mA IO = -24 mA ILI IOZ Ioff ICC ICC input leakage current 3-state output OFF-state current power OFF leakage current quiescent supply current additional quiescent supply current per input pin VI = 3.6 V or GND VI = VIH or VIL; VO = 3.6 V or GND; note 2 VI or VO = 3.6 V VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 3.6 3.6 0.0 3.6 3.0 to 3.6 VCC - 0.2 1.25 1.8 1.7 2.2 2.4 2.2 - - - - - - 1.51 2.10 2.01 2.53 2.76 2.68 0.1 0.1 0.1 0.2 5 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 - - - - - - - - 0.11 0.17 0.25 0.16 0.23 0.30 1.7 2 - - - - - - - VCC (V) MIN. TYP.(1)
74ALVC125
MAX.
UNIT
- - - 0.7 0.8 0.2 0.3 0.4 0.6 0.4 0.4 0.55 - - - - - - - 5 10 10 10 750
V V V V V V V V V V V V V V V V V V V A A A A A
1.65 to 1.95 -
0.35 x VCC V
Notes 1. All typical values are measured at Tamb = 25 C. 2. For transceivers, the parameter IOZ includes the input leakage current.
2002 Nov 18
6
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
AC CHARACTERISTICS TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +85 C tPHL/tPLH propagation delay input nA to output nY see Figs 5 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time input nOE to output nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tPHZ/tPLZ 3-state output disable time input nOE to output nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Note 1. All typical values are measured at Tamb = 25 C. AC WAVEFORMS 1.3 1.0 - 1.1 1.4 1.0 - 1.0 1.8 1.0 - 1.4 2.4 1.7 2.0 1.8 3.9 2.2 2.7 1.9 3.9 2.1 2.9 2.7 VCC (V) MIN. TYP.(1)
74ALVC125
MAX.
UNIT
5.3 3.2 3.1 2.8 6.4 4.1 4.3 3.5 5.9 3.4 4.0 4.0
ns ns ns ns ns ns ns ns ns ns ns ns
handbook, halfpage
VI VM GND tPHL VOH tPLH
nA input
nY output VOL
VM
MNA230
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V VCC VCC 2.7 V 2.7 V VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns
Fig.5 Input nA to output nY propagation delay times.
2002 Nov 18
7
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74ALVC125
handbook, full pagewidth
VI nOE input GND tPLZ output LOW-to-OFF OFF-to-LOW VCC VM VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
MNA654
VM
tPZL
Vx tPZH Vy VM
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V VCC VCC 2.7 V 2.7 V VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns
VX = VOL + 0.3 V at VCC 2.7 V; VX = VOL + 0.15 V at VCC < 2.7 V; VY = VOH - 0.3 V at VCC 2.7 V; VY = VOH - 0.15 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 3-state enable and disable times.
2002 Nov 18
8
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74ALVC125
handbook, full pagewidth
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
MNA616
VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V
VI VCC VCC 2.7 V 2.7 V
CL 30 pF 30 pF 50 pF 50 pF
RL 1 k 500 500 500
VEXT tPLH/tPHL tPZH/tPHZ open open open open GND GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 6V 6V
Definitions for test circuit RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2002 Nov 18
9
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm
74ALVC125
SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 A1 pin 1 index Lp 1 e bp 7 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.050 0.041 0.228 0.016
0.028 0.004 0.012
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
2002 Nov 18
10
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
74ALVC125
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27
2002 Nov 18
11
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
74ALVC125
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Nov 18
12
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
74ALVC125
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Nov 18
13
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74ALVC125
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Nov 18
14
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
NOTES
74ALVC125
2002 Nov 18
15
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/01/pp16
Date of release: 2002
Nov 18
Document order number:
9397 750 10451

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